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In additon, a "ready" signal is generated through the "Ready generator" and sent to the control logic of the ADC, which controls the switches in the DAC array and sends the "delay signal" to the comparator before the next comparison is made. POSTSUBSCRIPT, MSB) is generated and stored into the output registers. POSTSUBSCRIPT. Thus, a better linearity from the ADC output as well as code continuity can be achieved. When implementing only that functionality, the density clearly can and will be increased, though a constraint is provided by the need to reduce the settling time of the select logic tree employed. However, it consumes 27X more time as compared to the MAC unit, since it performs bit-level addition<br><br>Batch Normalization: This operation performs biasing of an input value in BNNs. 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